Implementation notes: riscv64, riscvunleashed000, crypto_hash/lane512

Computer: riscvunleashed000
Microarchitecture: riscv64; U54 (sifive,u54-mc)
Architecture: riscv64
CPU ID: unknown CPU ID
SUPERCOP version: 20240107
Operation: crypto_hash
Primitive: lane512
TimeObject sizeTest sizeImplementationCompilerBenchmark dateSUPERCOP version
49520690628 0 099201 776 728T:cclang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2024011320231222
49530190628 0 098781 776 728T:cclang_-march=rv64imafdc_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2024011320231222
49538190458 0 096957 768 721T:cclang_-march=rv64imafdc_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2024011320231222
49552390628 0 099201 776 728T:cclang_-march=rv64imafdc_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2024011320231222
49568690628 0 098781 776 728T:cclang_-march=rv64imafdc_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2024011320231222

Compiler output

Implementation: T:c
Security model: timingleaks
Compiler: gcc -mcpu=sifive-u54 -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE
lane.c: Alarm clock

Number of similar (compiler,implementation) pairs: 4, namely:
CompilerImplementations
gcc -mcpu=sifive-u54 -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE T:c
gcc -mcpu=sifive-u54 -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE T:c
gcc -mcpu=sifive-u54 -O -fomit-frame-pointer -fwrapv -fPIC -fPIE T:c
gcc -mcpu=sifive-u54 -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE T:c