Implementation notes: riscv64, riscvunleashed000, crypto_dh/hecfp61e2i

Computer: riscvunleashed000
Architecture: riscv64
CPU ID: unknown CPU ID
SUPERCOP version: 20210326
Operation: crypto_dh
Primitive: hecfp61e2i

Compiler output

Implementation: T:v01/var
Security model: timingleaks
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE
divisor_aadd.S: divisor_aadd.S:9:9: error: unrecognized operand modifier
divisor_aadd.S: pushq %r12
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:9:9: error: unknown operand
divisor_aadd.S: pushq %r12
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:10:9: error: unrecognized operand modifier
divisor_aadd.S: pushq %rbx
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:10:9: error: unknown operand
divisor_aadd.S: pushq %rbx
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:11:9: error: unrecognized operand modifier
divisor_aadd.S: pushq %r13
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:11:9: error: unknown operand
divisor_aadd.S: pushq %r13
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:12:7: error: unknown operand
divisor_aadd.S: movq $0x1FFFFFFFFFFFFFFF, %rsi
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:13:10: error: expected register
divisor_aadd.S: movq 48(%r8), %rax
divisor_aadd.S: ^
divisor_aadd.S: divisor_aadd.S:14:10: error: expected register
divisor_aadd.S: ...

Number of similar (compiler,implementation) pairs: 1, namely:
CompilerImplementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE T:v01/var

Compiler output

Implementation: T:v01/w8s01
Security model: timingleaks
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE
array_lo.c: array_lo.c:37:3: error: invalid output constraint '=&d' in asm
array_lo.c: mim_mul_1(an[al], an, an, al, base, buf[i]);
array_lo.c: ^
array_lo.c: ./multiprecision.h:696:4: note: expanded from macro 'mim_mul_1'
array_lo.c: km_mul_2_add_c(_t, (zn)[0], (an)[0], (b), _t); \
array_lo.c: ^
array_lo.c: ./kernel.h:127:4: note: expanded from macro 'km_mul_2_add_c'
array_lo.c: : "=&d"((zH)), "=a"((zL)) \
array_lo.c: ^
array_lo.c: array_lo.c:37:3: error: invalid output constraint '=&d' in asm
array_lo.c: ./multiprecision.h:699:4: note: expanded from macro 'mim_mul_1'
array_lo.c: km_mul_2_add_c(_t, (zn)[0], (an)[0], (b), _t); \
array_lo.c: ^
array_lo.c: ./kernel.h:127:4: note: expanded from macro 'km_mul_2_add_c'
array_lo.c: : "=&d"((zH)), "=a"((zL)) \
array_lo.c: ^
array_lo.c: array_lo.c:37:3: error: invalid output constraint '=&d' in asm
array_lo.c: ./multiprecision.h:700:4: note: expanded from macro 'mim_mul_1'
array_lo.c: km_mul_2_add_c(_t, (zn)[1], (an)[1], (b), _t); \
array_lo.c: ^
array_lo.c: ./kernel.h:127:4: note: expanded from macro 'km_mul_2_add_c'
array_lo.c: : "=&d"((zH)), "=a"((zL)) \
array_lo.c: ^
array_lo.c: array_lo.c:37:3: error: invalid output constraint '=&d' in asm
array_lo.c: ./multiprecision.h:703:4: note: expanded from macro 'mim_mul_1'
array_lo.c: ...

Number of similar (compiler,implementation) pairs: 6, namely:
CompilerImplementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE T:v01/w8s01 T:v01/w8s02 T:v01/w8s04 T:v01/w8s08 T:v01/w8s16 T:v01/w8s32