Implementation notes: armeabi, berry2, crypto_hash/asconhashbi32v12

Computer: berry2
Microarchitecture: armeabi; Cortex-A7 (410fc075)
Architecture: armeabi
CPU ID: unknown CPU ID
SUPERCOP version: 20240107
Operation: crypto_hash
Primitive: asconhashbi32v12

Time	Object size	Test size	Implementation	Compiler	Benchmark date	SUPERCOP version
131110	3168 0 0	10995 380 744	`bi32_armv6`	`gcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
131110	3168 0 0	12868 384 744	`bi32_armv6`	`gcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
131704	3276 0 0	22552 384 760	`bi32_armv6`	`clang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240123	20240107
132076	3156 0 0	10423 372 744	`bi32_armv6`	`gcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
135038	3384 0 0	11219 380 744	`bi32_armv6`	`gcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
175316	10160 0 0	19880 384 744	`ref`	`gcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
178153	4296 0 0	12115 380 744	`bi32`	`gcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
178186	4296 0 0	13996 384 744	`bi32`	`gcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
185686	10108 0 0	17951 380 744	`ref`	`gcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
186758	4308 0 0	11567 372 744	`bi32`	`gcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
199562	9904 0 0	17755 380 744	`ref`	`gcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
204163	2152 0 0	10003 384 744	`bi32_lowreg`	`gcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
204188	2188 0 0	11920 388 744	`bi32_lowreg`	`gcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
205450	948 0 0	10680 388 744	`bi32_lowsize`	`gcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
205464	948 0 0	8799 384 744	`bi32_lowsize`	`gcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
210902	4648 0 0	23918 384 760	`bi32`	`clang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240123	20240107
218149	4556 0 0	12383 380 744	`bi32`	`gcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
227382	940 0 0	8231 376 744	`bi32_lowsize`	`gcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
234086	1860 0 0	9151 376 744	`bi32_lowreg`	`gcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
263488	1176 0 0	9035 384 744	`bi32_lowsize`	`gcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
264032	2232 0 0	10091 384 744	`bi32_lowreg`	`gcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
279168	1056 0 0	8335 372 744	`ref`	`gcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20240123	20240107
291088	2572 0 0	21865 384 760	`ref`	`clang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240123	20240107
295522	2336 0 0	21621 388 760	`bi32_lowreg`	`clang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240123	20240107
305606	1156 0 0	20458 388 760	`bi32_lowsize`	`clang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20240123	20240107

Compiler output

Implementation: bi32_armv6m
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE

hash.c: In file included from hash.c:4:
hash.c: In file included from ./permutations.h:11:
hash.c: ./round.h:14:7: error: couldn't allocate output register for constraint 'h'
hash.c: "@.syntax_unified\n\t"
hash.c: ^
hash.c: ./round.h:14:7: error: couldn't allocate output register for constraint 'h'
hash.c: ./round.h:14:7: error: couldn't allocate output register for constraint 'h'
hash.c: ./round.h:14:7: error: couldn't allocate output register for constraint 'h'
hash.c: ./round.h:14:7: error: couldn't allocate output register for constraint 'h'
hash.c: 5 errors generated.

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	bi32_armv6m

Compiler output

Implementation: bi32_armv6m
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE

hash.c: In file included from permutations.h:11,
hash.c: from hash.c:4:
hash.c: hash.c: In function 'crypto_hash_asconhashbi32v12_bi32_armv6m_constbranchindex':
hash.c: round.h:13:3: error: impossible constraint in 'asm'
hash.c: __asm__ __volatile__(
hash.c: ^~~~~~~
hash.c: round.h:13:3: error: impossible constraint in 'asm'
hash.c: __asm__ __volatile__(
hash.c: ^~~~~~~
hash.c: round.h:13:3: error: impossible constraint in 'asm'
hash.c: __asm__ __volatile__(
hash.c: ^~~~~~~

Number of similar (compiler,implementation) pairs: 4, namely:

Compiler	Implementations
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6m
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6m
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6m
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6m

Compiler output

Implementation: bi32_armv7m
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE

hash.c: In file included from hash.c:4:
hash.c: ./permutations.h:34:3: error: instruction requires: thumb2
hash.c: ROUND5(x0, x1, x2, x3, x4, RC0);
hash.c: ^
hash.c: ./round.h:159:41: note: expanded from macro 'ROUND5'
hash.c: "eor %[tmp2], %[x3_l], %[x4_l]\n\t" \
hash.c: ^
hash.c: <inline asm>:5:2: note: instantiated into assembly here
hash.c: orn r11, r8, r11
hash.c: ^
hash.c: In file included from hash.c:4:
hash.c: ./permutations.h:34:3: error: instruction requires: thumb2
hash.c: ROUND5(x0, x1, x2, x3, x4, RC0);
hash.c: ^
hash.c: ./round.h:175:41: note: expanded from macro 'ROUND5'
hash.c: "eor %[tmp2], %[x3_h], %[x4_h]\n\t" \
hash.c: ^
hash.c: <inline asm>:21:2: note: instantiated into assembly here
hash.c: orn r7, r1, r7
hash.c: ^
hash.c: In file included from hash.c:4:
hash.c: ./permutations.h:35:3: error: instruction requires: thumb2
hash.c: ROUND5(x2, x3, x4, x0, x1, RC1);
hash.c: ^
hash.c: ./round.h:159:41: note: expanded from macro 'ROUND5'
hash.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	bi32_armv7m

Compiler output

Implementation: bi32_armv7m
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE

hash.c: /tmp/ccjS9DP6.s: Assembler messages:
hash.c: /tmp/ccjS9DP6.s:82: Error: selected processor does not support `orn r0,lr,r0' in ARM mode
hash.c: /tmp/ccjS9DP6.s:98: Error: selected processor does not support `orn r1,ip,r1' in ARM mode
hash.c: /tmp/ccjS9DP6.s:137: Error: selected processor does not support `orn r7,r2,r7' in ARM mode
hash.c: /tmp/ccjS9DP6.s:153: Error: selected processor does not support `orn r6,r3,r6' in ARM mode
hash.c: /tmp/ccjS9DP6.s:192: Error: selected processor does not support `orn lr,r5,lr' in ARM mode
hash.c: /tmp/ccjS9DP6.s:208: Error: selected processor does not support `orn ip,r4,ip' in ARM mode
hash.c: /tmp/ccjS9DP6.s:247: Error: selected processor does not support `orn r2,r0,r2' in ARM mode
hash.c: /tmp/ccjS9DP6.s:263: Error: selected processor does not support `orn r3,r1,r3' in ARM mode
hash.c: /tmp/ccjS9DP6.s:302: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/ccjS9DP6.s:318: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/ccjS9DP6.s:357: Error: selected processor does not support `orn r0,lr,r0' in ARM mode
hash.c: /tmp/ccjS9DP6.s:373: Error: selected processor does not support `orn r1,ip,r1' in ARM mode
hash.c: /tmp/ccjS9DP6.s:412: Error: selected processor does not support `orn r7,r2,r7' in ARM mode
hash.c: /tmp/ccjS9DP6.s:428: Error: selected processor does not support `orn r6,r3,r6' in ARM mode
hash.c: /tmp/ccjS9DP6.s:467: Error: selected processor does not support `orn lr,r5,lr' in ARM mode
hash.c: /tmp/ccjS9DP6.s:483: Error: selected processor does not support `orn ip,r4,ip' in ARM mode
hash.c: /tmp/ccjS9DP6.s:522: Error: selected processor does not support `orn r2,r0,r2' in ARM mode
hash.c: /tmp/ccjS9DP6.s:538: Error: selected processor does not support `orn r3,r1,r3' in ARM mode
hash.c: /tmp/ccjS9DP6.s:577: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/ccjS9DP6.s:593: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/ccjS9DP6.s:631: Error: selected processor does not support `orn r9,r0,r2' in ARM mode
hash.c: /tmp/ccjS9DP6.s:635: Error: selected processor does not support `orn r10,lr,r0' in ARM mode
hash.c: /tmp/ccjS9DP6.s:649: Error: selected processor does not support `orn r9,r1,r3' in ARM mode
hash.c: /tmp/ccjS9DP6.s:652: Error: selected processor does not support `orn r10,ip,r1' in ARM mode
hash.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m

Compiler output

Implementation: bi32_armv7m
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE

hash.c: /tmp/ccDH8t9U.s: Assembler messages:
hash.c: /tmp/ccDH8t9U.s:82: Error: selected processor does not support `orn r0,lr,r0' in ARM mode
hash.c: /tmp/ccDH8t9U.s:98: Error: selected processor does not support `orn r1,ip,r1' in ARM mode
hash.c: /tmp/ccDH8t9U.s:137: Error: selected processor does not support `orn r7,r2,r7' in ARM mode
hash.c: /tmp/ccDH8t9U.s:153: Error: selected processor does not support `orn r6,r3,r6' in ARM mode
hash.c: /tmp/ccDH8t9U.s:192: Error: selected processor does not support `orn lr,r5,lr' in ARM mode
hash.c: /tmp/ccDH8t9U.s:208: Error: selected processor does not support `orn ip,r4,ip' in ARM mode
hash.c: /tmp/ccDH8t9U.s:247: Error: selected processor does not support `orn r2,r0,r2' in ARM mode
hash.c: /tmp/ccDH8t9U.s:263: Error: selected processor does not support `orn r3,r1,r3' in ARM mode
hash.c: /tmp/ccDH8t9U.s:302: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/ccDH8t9U.s:318: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/ccDH8t9U.s:357: Error: selected processor does not support `orn r0,lr,r0' in ARM mode
hash.c: /tmp/ccDH8t9U.s:373: Error: selected processor does not support `orn r1,ip,r1' in ARM mode
hash.c: /tmp/ccDH8t9U.s:412: Error: selected processor does not support `orn r7,r2,r7' in ARM mode
hash.c: /tmp/ccDH8t9U.s:428: Error: selected processor does not support `orn r6,r3,r6' in ARM mode
hash.c: /tmp/ccDH8t9U.s:467: Error: selected processor does not support `orn lr,r5,lr' in ARM mode
hash.c: /tmp/ccDH8t9U.s:483: Error: selected processor does not support `orn ip,r4,ip' in ARM mode
hash.c: /tmp/ccDH8t9U.s:522: Error: selected processor does not support `orn r2,r0,r2' in ARM mode
hash.c: /tmp/ccDH8t9U.s:538: Error: selected processor does not support `orn r3,r1,r3' in ARM mode
hash.c: /tmp/ccDH8t9U.s:577: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/ccDH8t9U.s:593: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/ccDH8t9U.s:631: Error: selected processor does not support `orn r9,r0,r2' in ARM mode
hash.c: /tmp/ccDH8t9U.s:635: Error: selected processor does not support `orn r10,lr,r0' in ARM mode
hash.c: /tmp/ccDH8t9U.s:649: Error: selected processor does not support `orn r9,r1,r3' in ARM mode
hash.c: /tmp/ccDH8t9U.s:652: Error: selected processor does not support `orn r10,ip,r1' in ARM mode
hash.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m

Compiler output

Implementation: bi32_armv7m
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE

hash.c: /tmp/cc5VNQBo.s: Assembler messages:
hash.c: /tmp/cc5VNQBo.s:93: Error: selected processor does not support `orn r0,lr,r0' in ARM mode
hash.c: /tmp/cc5VNQBo.s:109: Error: selected processor does not support `orn r1,ip,r1' in ARM mode
hash.c: /tmp/cc5VNQBo.s:148: Error: selected processor does not support `orn r7,r2,r7' in ARM mode
hash.c: /tmp/cc5VNQBo.s:164: Error: selected processor does not support `orn r6,r3,r6' in ARM mode
hash.c: /tmp/cc5VNQBo.s:203: Error: selected processor does not support `orn lr,r5,lr' in ARM mode
hash.c: /tmp/cc5VNQBo.s:219: Error: selected processor does not support `orn ip,r4,ip' in ARM mode
hash.c: /tmp/cc5VNQBo.s:258: Error: selected processor does not support `orn r2,r0,r2' in ARM mode
hash.c: /tmp/cc5VNQBo.s:274: Error: selected processor does not support `orn r3,r1,r3' in ARM mode
hash.c: /tmp/cc5VNQBo.s:313: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/cc5VNQBo.s:329: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/cc5VNQBo.s:368: Error: selected processor does not support `orn r0,lr,r0' in ARM mode
hash.c: /tmp/cc5VNQBo.s:384: Error: selected processor does not support `orn r1,ip,r1' in ARM mode
hash.c: /tmp/cc5VNQBo.s:423: Error: selected processor does not support `orn r7,r2,r7' in ARM mode
hash.c: /tmp/cc5VNQBo.s:439: Error: selected processor does not support `orn r6,r3,r6' in ARM mode
hash.c: /tmp/cc5VNQBo.s:478: Error: selected processor does not support `orn lr,r5,lr' in ARM mode
hash.c: /tmp/cc5VNQBo.s:494: Error: selected processor does not support `orn ip,r4,ip' in ARM mode
hash.c: /tmp/cc5VNQBo.s:533: Error: selected processor does not support `orn r2,r0,r2' in ARM mode
hash.c: /tmp/cc5VNQBo.s:549: Error: selected processor does not support `orn r3,r1,r3' in ARM mode
hash.c: /tmp/cc5VNQBo.s:588: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/cc5VNQBo.s:604: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/cc5VNQBo.s:642: Error: selected processor does not support `orn r9,r0,r2' in ARM mode
hash.c: /tmp/cc5VNQBo.s:646: Error: selected processor does not support `orn r10,lr,r0' in ARM mode
hash.c: /tmp/cc5VNQBo.s:660: Error: selected processor does not support `orn r9,r1,r3' in ARM mode
hash.c: /tmp/cc5VNQBo.s:663: Error: selected processor does not support `orn r10,ip,r1' in ARM mode
hash.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m

Compiler output

Implementation: bi32_armv7m
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE

hash.c: /tmp/ccQUMlg9.s: Assembler messages:
hash.c: /tmp/ccQUMlg9.s:117: Error: selected processor does not support `orn lr,r4,lr' in ARM mode
hash.c: /tmp/ccQUMlg9.s:133: Error: selected processor does not support `orn ip,r2,ip' in ARM mode
hash.c: /tmp/ccQUMlg9.s:172: Error: selected processor does not support `orn r8,fp,r8' in ARM mode
hash.c: /tmp/ccQUMlg9.s:188: Error: selected processor does not support `orn r7,r3,r7' in ARM mode
hash.c: /tmp/ccQUMlg9.s:227: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/ccQUMlg9.s:243: Error: selected processor does not support `orn r2,r5,r2' in ARM mode
hash.c: /tmp/ccQUMlg9.s:282: Error: selected processor does not support `orn fp,lr,fp' in ARM mode
hash.c: /tmp/ccQUMlg9.s:298: Error: selected processor does not support `orn r3,ip,r3' in ARM mode
hash.c: /tmp/ccQUMlg9.s:337: Error: selected processor does not support `orn r6,r8,r6' in ARM mode
hash.c: /tmp/ccQUMlg9.s:353: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/ccQUMlg9.s:392: Error: selected processor does not support `orn lr,r4,lr' in ARM mode
hash.c: /tmp/ccQUMlg9.s:408: Error: selected processor does not support `orn ip,r2,ip' in ARM mode
hash.c: /tmp/ccQUMlg9.s:447: Error: selected processor does not support `orn r8,fp,r8' in ARM mode
hash.c: /tmp/ccQUMlg9.s:463: Error: selected processor does not support `orn r7,r3,r7' in ARM mode
hash.c: /tmp/ccQUMlg9.s:502: Error: selected processor does not support `orn r4,r6,r4' in ARM mode
hash.c: /tmp/ccQUMlg9.s:518: Error: selected processor does not support `orn r2,r5,r2' in ARM mode
hash.c: /tmp/ccQUMlg9.s:557: Error: selected processor does not support `orn fp,lr,fp' in ARM mode
hash.c: /tmp/ccQUMlg9.s:573: Error: selected processor does not support `orn r3,ip,r3' in ARM mode
hash.c: /tmp/ccQUMlg9.s:612: Error: selected processor does not support `orn r6,r8,r6' in ARM mode
hash.c: /tmp/ccQUMlg9.s:628: Error: selected processor does not support `orn r5,r7,r5' in ARM mode
hash.c: /tmp/ccQUMlg9.s:666: Error: selected processor does not support `orn r1,lr,fp' in ARM mode
hash.c: /tmp/ccQUMlg9.s:670: Error: selected processor does not support `orn r0,r4,lr' in ARM mode
hash.c: /tmp/ccQUMlg9.s:684: Error: selected processor does not support `orn r1,ip,r3' in ARM mode
hash.c: /tmp/ccQUMlg9.s:687: Error: selected processor does not support `orn r0,r2,ip' in ARM mode
hash.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m

Compiler output

Implementation: bi32_armv7m_small
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE

permutations.c: In file included from permutations.c:1:
permutations.c: In file included from ./permutations.h:11:
permutations.c: ./round.h:18:39: error: instruction requires: thumb2
permutations.c: "eor %[x2_l], %[x2_l], %[x1_l]\n\t"
permutations.c: ^
permutations.c: <inline asm>:6:2: note: instantiated into assembly here
permutations.c: orn r2, r10, r12
permutations.c: ^
permutations.c: In file included from permutations.c:1:
permutations.c: In file included from ./permutations.h:11:
permutations.c: ./round.h:22:39: error: instruction requires: thumb2
permutations.c: "eor %[x0_l], %[x0_l], %[tmp1]\n\t"
permutations.c: ^
permutations.c: <inline asm>:10:2: note: instantiated into assembly here
permutations.c: orn r9, r7, r10
permutations.c: ^
permutations.c: In file included from permutations.c:1:
permutations.c: In file included from ./permutations.h:11:
permutations.c: ./round.h:37:39: error: instruction requires: thumb2
permutations.c: "eor %[x2_h], %[x2_h], %[x1_h]\n\t"
permutations.c: ^
permutations.c: <inline asm>:25:2: note: instantiated into assembly here
permutations.c: orn r2, r11, r0
permutations.c: ^
permutations.c: In file included from permutations.c:1:
permutations.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	bi32_armv7m_small

Compiler output

Implementation: bi32_armv7m_small
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE

permutations.c: /tmp/ccbT3jjU.s: Assembler messages:
permutations.c: /tmp/ccbT3jjU.s:56: Error: selected processor does not support `orn r1,r2,r9' in ARM mode
permutations.c: /tmp/ccbT3jjU.s:60: Error: selected processor does not support `orn r0,lr,r2' in ARM mode
permutations.c: /tmp/ccbT3jjU.s:75: Error: selected processor does not support `orn r1,r3,r8' in ARM mode
permutations.c: /tmp/ccbT3jjU.s:78: Error: selected processor does not support `orn r0,ip,r3' in ARM mode

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m_small

Compiler output

Implementation: bi32_armv7m_small
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE

permutations.c: /tmp/ccMg7taq.s: Assembler messages:
permutations.c: /tmp/ccMg7taq.s:56: Error: selected processor does not support `orn r1,r2,r9' in ARM mode
permutations.c: /tmp/ccMg7taq.s:60: Error: selected processor does not support `orn r0,lr,r2' in ARM mode
permutations.c: /tmp/ccMg7taq.s:75: Error: selected processor does not support `orn r1,r3,r8' in ARM mode
permutations.c: /tmp/ccMg7taq.s:78: Error: selected processor does not support `orn r0,ip,r3' in ARM mode

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m_small

Compiler output

Implementation: bi32_armv7m_small
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE

permutations.c: /tmp/ccqG1w3l.s: Assembler messages:
permutations.c: /tmp/ccqG1w3l.s:56: Error: selected processor does not support `orn r0,ip,r10' in ARM mode
permutations.c: /tmp/ccqG1w3l.s:60: Error: selected processor does not support `orn fp,r4,ip' in ARM mode
permutations.c: /tmp/ccqG1w3l.s:75: Error: selected processor does not support `orn r0,r2,r9' in ARM mode
permutations.c: /tmp/ccqG1w3l.s:78: Error: selected processor does not support `orn fp,lr,r2' in ARM mode

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m_small

Compiler output

Implementation: bi32_armv7m_small
Security model: constbranchindex
Compiler: gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE

permutations.c: /tmp/cciDBxJe.s: Assembler messages:
permutations.c: /tmp/cciDBxJe.s:55: Error: selected processor does not support `orn r0,ip,r10' in ARM mode
permutations.c: /tmp/cciDBxJe.s:59: Error: selected processor does not support `orn fp,r4,ip' in ARM mode
permutations.c: /tmp/cciDBxJe.s:74: Error: selected processor does not support `orn r0,r2,r9' in ARM mode
permutations.c: /tmp/cciDBxJe.s:77: Error: selected processor does not support `orn fp,lr,r2' in ARM mode

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv7m_small

Namespace violations

Implementation: bi32
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE

constants.o constants R
permutations.o P12 T

Number of similar (compiler,implementation) pairs: 10, namely:

Compiler	Implementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	bi32
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	bi32_armv6
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_armv6

Namespace violations

Implementation: bi32_lowreg
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE

constants.o constants R
hash.o ascon_absorb T
hash.o ascon_inithash T
hash.o ascon_squeeze T

Number of similar (compiler,implementation) pairs: 5, namely:

Compiler	Implementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	bi32_lowreg
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowreg
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowreg
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowreg
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowreg

Namespace violations

Implementation: bi32_lowsize
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE

constants.o constants R
permutations.o P T

Number of similar (compiler,implementation) pairs: 5, namely:

Compiler	Implementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	bi32_lowsize
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowsize
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowsize
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowsize
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	bi32_lowsize