Implementation notes: amd64, titan0, crypto_core/multsntrup1277

Computer: titan0
Architecture: amd64
CPU ID: GenuineIntel-000306c3-bfebfbff
SUPERCOP version: 20211108
Operation: crypto_core
Primitive: multsntrup1277
TimeObject sizeTest sizeImplementationCompilerBenchmark dateSUPERCOP version
3054721977 0 037665 804 976avxgcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
3058021977 0 037665 804 976avx800gcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
3260822552 0 037507 820 944avxclang_-march=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3270722520 0 037475 820 944avxclang_-march=native_-O_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3272422520 0 037475 820 944avxclang_-march=native_-O2_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3287822408 0 037363 820 944avx800clang_-march=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3288022408 0 037363 820 944avx800clang_-march=native_-O2_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3288722408 0 037363 820 944avx800clang_-march=native_-O_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3408221820 0 034208 796 976avxgcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
3430621764 0 034160 796 976avx800gcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
3588721384 0 032513 812 912avxclang_-march=native_-Os_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3602821421 0 032561 812 912avx800clang_-march=native_-Os_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3669121841 0 034320 796 976avxgcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
3702921841 0 034320 796 976avx800gcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
4163822637 0 034152 788 944avx800gcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
4186922648 0 034160 788 944avxgcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
5558502274 0 017323 820 944refclang_-march=native_-O_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
5602153410 0 018491 820 944refclang_-march=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
5753332274 0 017323 820 944refclang_-march=native_-O2_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
6045714626 0 020297 804 976refgcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
21028302703 0 017035 820 912refclang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
2575780620 0 011841 812 912refclang_-march=native_-Os_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE2021053020210529
3199490596 0 012952 796 976refgcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
3778630669 0 013104 796 976refgcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529
3890210527 0 011976 788 944refgcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE2021053020210529

Compiler output

Implementation: avx
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE
mult1280.c: mult1280.c:425:7: error: always_inline function '_mm256_set1_epi16' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: x = const_x16(0);
mult1280.c: ^
mult1280.c: mult1280.c:10:19: note: expanded from macro 'const_x16'
mult1280.c: #define const_x16 _mm256_set1_epi16
mult1280.c: ^
mult1280.c: mult1280.c:426:36: error: always_inline function '_mm256_storeu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: for (i = p&~15;i < 1280;i += 16) store_x16(&f[i],x);
mult1280.c: ^
mult1280.c: mult1280.c:9:24: note: expanded from macro 'store_x16'
mult1280.c: #define store_x16(p,v) _mm256_storeu_si256((int16x16 *) (p),(v))
mult1280.c: ^
mult1280.c: mult1280.c:427:36: error: always_inline function '_mm256_storeu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: for (i = p&~15;i < 1280;i += 16) store_x16(&g[i],x);
mult1280.c: ^
mult1280.c: mult1280.c:9:24: note: expanded from macro 'store_x16'
mult1280.c: #define store_x16(p,v) _mm256_storeu_si256((int16x16 *) (p),(v))
mult1280.c: ^
mult1280.c: mult1280.c:432:9: error: always_inline function '_mm256_loadu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: x = load_x16(&f[i]);
mult1280.c: ^
mult1280.c: mult1280.c:8:21: note: expanded from macro 'load_x16'
mult1280.c: #define load_x16(p) _mm256_loadu_si256((int16x16 *) (p))
mult1280.c: ^
mult1280.c: mult1280.c:434:5: error: always_inline function '_mm256_storeu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:
CompilerImplementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE avx

Compiler output

Implementation: avx800
Security model: constbranchindex
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE
mult1280.c: mult1280.c:425:7: error: always_inline function '_mm256_set1_epi16' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx800_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: x = const_x16(0);
mult1280.c: ^
mult1280.c: mult1280.c:10:19: note: expanded from macro 'const_x16'
mult1280.c: #define const_x16 _mm256_set1_epi16
mult1280.c: ^
mult1280.c: mult1280.c:426:36: error: always_inline function '_mm256_storeu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx800_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: for (i = p&~15;i < 1280;i += 16) store_x16(&f[i],x);
mult1280.c: ^
mult1280.c: mult1280.c:9:24: note: expanded from macro 'store_x16'
mult1280.c: #define store_x16(p,v) _mm256_storeu_si256((int16x16 *) (p),(v))
mult1280.c: ^
mult1280.c: mult1280.c:427:36: error: always_inline function '_mm256_storeu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx800_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: for (i = p&~15;i < 1280;i += 16) store_x16(&g[i],x);
mult1280.c: ^
mult1280.c: mult1280.c:9:24: note: expanded from macro 'store_x16'
mult1280.c: #define store_x16(p,v) _mm256_storeu_si256((int16x16 *) (p),(v))
mult1280.c: ^
mult1280.c: mult1280.c:432:9: error: always_inline function '_mm256_loadu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx800_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: x = load_x16(&f[i]);
mult1280.c: ^
mult1280.c: mult1280.c:8:21: note: expanded from macro 'load_x16'
mult1280.c: #define load_x16(p) _mm256_loadu_si256((int16x16 *) (p))
mult1280.c: ^
mult1280.c: mult1280.c:434:5: error: always_inline function '_mm256_storeu_si256' requires target feature 'sse4.2', but would be inlined into function 'crypto_core_multsntrup1277_avx800_constbranchindex' that is compiled without support for 'sse4.2'
mult1280.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:
CompilerImplementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE avx800