Implementation notes: aarch64, pi3aplus, crypto_hash/lane256

Computer: pi3aplus
Microarchitecture: aarch64; Cortex-A53 (410fd034)
Architecture: aarch64
CPU ID: 410fd034
SUPERCOP version: 20231107
Operation: crypto_hash
Primitive: lane256

Time	Object size	Test size	Implementation	Compiler	Benchmark date	SUPERCOP version
86100	79344 0 0	90549 768 736	`T:c`	`clang_-mcpu=native_-O3_-fomit-frame-pointer_-fwrapv_-Qunused-arguments_-fPIC_-fPIE`	20220530	20220506
90058	104080 0 0	114632 840 744	`T:c`	`gcc_-march=native_-mtune=native_-O3_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20220530	20220506
90133	103876 0 0	113200 840 728	`T:c`	`gcc_-march=native_-mtune=native_-O2_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20220530	20220506
106017	80888 0 0	89280 824 720	`T:c`	`gcc_-march=native_-mtune=native_-Os_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20220530	20220506
143945	82748 0 0	91992 840 728	`T:c`	`gcc_-march=native_-mtune=native_-O_-fomit-frame-pointer_-fwrapv_-fPIC_-fPIE`	20220530	20220506

Namespace violations

Implementation: T:c
Security model: timingleaks
Compiler: clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE

lane.o Final T
lane.o Hash T
lane.o Init T
lane.o Update T
lane.o lane256_compress T
lane.o lane512_compress T

Number of similar (compiler,implementation) pairs: 5, namely:

Compiler	Implementations
clang -mcpu=native -O3 -fomit-frame-pointer -fwrapv -Qunused-arguments -fPIC -fPIE	T:c
gcc -march=native -mtune=native -O2 -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c
gcc -march=native -mtune=native -O3 -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c
gcc -march=native -mtune=native -O -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c
gcc -march=native -mtune=native -Os -fomit-frame-pointer -fwrapv -fPIC -fPIE	T:c