Implementation notes: mipso32, h1mips, crypto_aead/omdsha256k192n104tau128v1

Computer: h1mips
Architecture: mipso32
CPU ID: unknown CPU ID
SUPERCOP version: 20140622
Operation: crypto_aead
Primitive: omdsha256k192n104tau128v1

Time	Implementation	Compiler	Benchmark date	SUPERCOP version
920030	`ref`	`gcc -funroll-loops -O3 -fomit-frame-pointer`	20140602	20140525
920040	`ref`	`gcc -funroll-loops -mabi=32 -O3 -fomit-frame-pointer`	20140602	20140525
923124	`ref`	`gcc -funroll-loops -fno-schedule-insns -O3 -fomit-frame-pointer`	20140602	20140525
927910	`ref`	`gcc -fno-schedule-insns -O3 -fomit-frame-pointer`	20140602	20140525
934590	`ref`	`gcc -mabi=32 -O3 -fomit-frame-pointer`	20140602	20140525
934602	`ref`	`gcc -O3 -fomit-frame-pointer`	20140602	20140525
1027156	`ref`	`gcc -funroll-loops -fno-schedule-insns -O2 -fomit-frame-pointer`	20140602	20140525
1036160	`ref`	`gcc -funroll-loops -O2 -fomit-frame-pointer`	20140602	20140525
1037228	`ref`	`gcc -funroll-loops -mabi=32 -O2 -fomit-frame-pointer`	20140602	20140525
1088802	`ref`	`gcc -mabi=32 -O2 -fomit-frame-pointer`	20140602	20140525
1088892	`ref`	`gcc -O2 -fomit-frame-pointer`	20140602	20140525
1094290	`ref`	`gcc -fno-schedule-insns -O2 -fomit-frame-pointer`	20140602	20140525
1109924	`ref`	`gcc -funroll-loops -fno-schedule-insns -O -fomit-frame-pointer`	20140602	20140525
1109950	`ref`	`gcc -funroll-loops -O -fomit-frame-pointer`	20140602	20140525
1110504	`ref`	`gcc -funroll-loops -mabi=32 -O -fomit-frame-pointer`	20140602	20140525
1158548	`ref`	`gcc -fno-schedule-insns -Os -fomit-frame-pointer`	20140602	20140525
1161208	`ref`	`gcc -funroll-loops -fno-schedule-insns -Os -fomit-frame-pointer`	20140602	20140525
1183898	`ref`	`gcc -mabi=32 -O -fomit-frame-pointer`	20140602	20140525
1183902	`ref`	`gcc -fno-schedule-insns -O -fomit-frame-pointer`	20140602	20140525
1184194	`ref`	`gcc -O -fomit-frame-pointer`	20140602	20140525
1234074	`ref`	`gcc -funroll-loops -mabi=32 -Os -fomit-frame-pointer`	20140602	20140525
1234996	`ref`	`gcc -funroll-loops -Os -fomit-frame-pointer`	20140602	20140525
1235038	`ref`	`gcc -Os -fomit-frame-pointer`	20140602	20140525
1235678	`ref`	`gcc -mabi=32 -Os -fomit-frame-pointer`	20140602	20140525
2884144	`ref`	`gcc -funroll-loops`	20140602	20140525
2884186	`ref`	`cc`	20140602	20140525
2884200	`ref`	`gcc`	20140602	20140525

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '+' is not a recognized feature for this target (ignoring feature)
encrypt.c: /tmp/cc-S7SmbR.s: Assembler messages:
encrypt.c: /tmp/cc-S7SmbR.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-S7SmbR.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-S7SmbR.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-S7SmbR.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '+' is not a recognized feature for this target (ignoring feature)
omdsha256.c: /tmp/cc-Tovn7b.s: Assembler messages:
omdsha256.c: /tmp/cc-Tovn7b.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-Tovn7b.s:826: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-Tovn7b.s:826: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=neon -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-Iu0ojy.s: Assembler messages:
encrypt.c: /tmp/cc-Iu0ojy.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-Iu0ojy.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-Iu0ojy.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-Iu0ojy.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-DqNNsT.s: Assembler messages:
omdsha256.c: /tmp/cc-DqNNsT.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DqNNsT.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DqNNsT.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=neon -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=neon -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-3BsxSw.s: Assembler messages:
encrypt.c: /tmp/cc-3BsxSw.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-3BsxSw.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-3BsxSw.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-3BsxSw.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-aFalQR.s: Assembler messages:
omdsha256.c: /tmp/cc-aFalQR.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-aFalQR.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-aFalQR.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=neon -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=vfpv3-d16 -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-CJVQ6w.s: Assembler messages:
encrypt.c: /tmp/cc-CJVQ6w.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-CJVQ6w.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-CJVQ6w.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-CJVQ6w.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-VOPzBS.s: Assembler messages:
omdsha256.c: /tmp/cc-VOPzBS.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-VOPzBS.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-VOPzBS.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=vfpv3-d16 -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=vfpv3-d16 -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-MRhlkg.s: Assembler messages:
encrypt.c: /tmp/cc-MRhlkg.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-MRhlkg.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-MRhlkg.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-MRhlkg.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-t8F1yu.s: Assembler messages:
omdsha256.c: /tmp/cc-t8F1yu.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-t8F1yu.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-t8F1yu.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=hard -mfpu=vfpv3-d16 -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-7iD53g.s: Assembler messages:
encrypt.c: /tmp/cc-7iD53g.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-7iD53g.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-7iD53g.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-7iD53g.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-z9Ub6t.s: Assembler messages:
omdsha256.c: /tmp/cc-z9Ub6t.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-z9Ub6t.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-z9Ub6t.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-sXQEyU.s: Assembler messages:
encrypt.c: /tmp/cc-sXQEyU.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-sXQEyU.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-sXQEyU.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-sXQEyU.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-q8ku1f.s: Assembler messages:
omdsha256.c: /tmp/cc-q8ku1f.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-q8ku1f.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-q8ku1f.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=neon -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=vfpv3-d16 -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-FyLxnT.s: Assembler messages:
encrypt.c: /tmp/cc-FyLxnT.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-FyLxnT.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-FyLxnT.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-FyLxnT.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-sqqOKe.s: Assembler messages:
omdsha256.c: /tmp/cc-sqqOKe.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-sqqOKe.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-sqqOKe.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=vfpv3-d16 -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=vfpv3-d16 -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-cnkiTv.s: Assembler messages:
encrypt.c: /tmp/cc-cnkiTv.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-cnkiTv.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-cnkiTv.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-cnkiTv.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-5oVUpR.s: Assembler messages:
omdsha256.c: /tmp/cc-5oVUpR.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-5oVUpR.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-5oVUpR.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=armv7-a -mfloat-abi=softfp -mfpu=vfpv3-d16 -fomit-frame-pointer -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=native -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-JdaSsv.s: Assembler messages:
encrypt.c: /tmp/cc-JdaSsv.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-JdaSsv.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-JdaSsv.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-JdaSsv.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-gcVvQQ.s: Assembler messages:
omdsha256.c: /tmp/cc-gcVvQQ.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-gcVvQQ.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-gcVvQQ.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=native -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -march=native -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: '+0' is not a recognized feature for this target (ignoring feature)
encrypt.c: '0' is not a recognized processor for this target (ignoring processor)
encrypt.c: /tmp/cc-VQk0ik.s: Assembler messages:
encrypt.c: /tmp/cc-VQk0ik.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-VQk0ik.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-VQk0ik.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-VQk0ik.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: '+0' is not a recognized feature for this target (ignoring feature)
omdsha256.c: '0' is not a recognized processor for this target (ignoring processor)
omdsha256.c: /tmp/cc-HHBEKt.s: Assembler messages:
omdsha256.c: /tmp/cc-HHBEKt.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-HHBEKt.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-HHBEKt.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -march=native -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -mavx2 -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '+' is not a recognized feature for this target (ignoring feature)
encrypt.c: /tmp/cc-1lHVCb.s: Assembler messages:
encrypt.c: /tmp/cc-1lHVCb.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-1lHVCb.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-1lHVCb.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-1lHVCb.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '+' is not a recognized feature for this target (ignoring feature)
omdsha256.c: /tmp/cc-iQNckx.s: Assembler messages:
omdsha256.c: /tmp/cc-iQNckx.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-iQNckx.s:826: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-iQNckx.s:826: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -mavx2 -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -mavx2 -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '+' is not a recognized feature for this target (ignoring feature)
encrypt.c: /tmp/cc-luyJ0c.s: Assembler messages:
encrypt.c: /tmp/cc-luyJ0c.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-luyJ0c.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-luyJ0c.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-luyJ0c.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '+' is not a recognized feature for this target (ignoring feature)
omdsha256.c: /tmp/cc-XbDqRn.s: Assembler messages:
omdsha256.c: /tmp/cc-XbDqRn.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-XbDqRn.s:826: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-XbDqRn.s:826: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -mavx2 -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -mavx -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '+' is not a recognized feature for this target (ignoring feature)
encrypt.c: /tmp/cc-Xbexl0.s: Assembler messages:
encrypt.c: /tmp/cc-Xbexl0.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-Xbexl0.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-Xbexl0.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-Xbexl0.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '+' is not a recognized feature for this target (ignoring feature)
omdsha256.c: /tmp/cc-DvHRWd.s: Assembler messages:
omdsha256.c: /tmp/cc-DvHRWd.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-DvHRWd.s:826: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-DvHRWd.s:826: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -mavx -fomit-frame-pointer	ref

Compiler output

Implementation: crypto_aead/omdsha256k192n104tau128v1/ref
Compiler: clang -O3 -fwrapv -mavx -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive -fomit-frame-pointer

encrypt.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
encrypt.c: '+' is not a recognized feature for this target (ignoring feature)
encrypt.c: /tmp/cc-RZNDfm.s: Assembler messages:
encrypt.c: /tmp/cc-RZNDfm.s:40: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-RZNDfm.s:40: Warning: Macro instruction expanded into multiple instructions
encrypt.c: /tmp/cc-RZNDfm.s:107: Warning: No .cprestore pseudo-op used in PIC code
encrypt.c: /tmp/cc-RZNDfm.s:107: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: clang: warning: unknown platform, assuming -mfloat-abi=soft
omdsha256.c: '+' is not a recognized feature for this target (ignoring feature)
omdsha256.c: /tmp/cc-SV5wVI.s: Assembler messages:
omdsha256.c: /tmp/cc-SV5wVI.s:166: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:166: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:217: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:217: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:222: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:222: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:227: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:227: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:264: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:264: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:427: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:427: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:633: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:633: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:731: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:731: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:740: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:740: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:745: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:745: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: /tmp/cc-SV5wVI.s:826: Warning: No .cprestore pseudo-op used in PIC code
omdsha256.c: /tmp/cc-SV5wVI.s:826: Warning: Macro instruction expanded into multiple instructions
omdsha256.c: ...

Number of similar (compiler,implementation) pairs: 1, namely:

Compiler	Implementations
clang -O3 -fwrapv -mavx -fpolly -funroll-loops -fvectorize -fslp-vectorize -fslp-vectorize-aggressive -fomit-frame-pointer	ref